1. Field of the Invention
The present invention relates in general to an repairing arrangement for a memory device, and more particularly to a address decoder for repair of a memory device, in which a failure of the memory device can efficiently be repaired.
2. Description of the Prior Art
It is common that a memory device such as, for example, a dynamic random access memory (DRAM) comprises redundant cell columns to guard against the case where at least one of the cell columns of a memory cell matrix has failed. For example, when one cell column of the memory cell matrix is failed, it is replaced with one of the redundant cell columns. In order to replace the failed memory cell column with the redundant cell column, it is necessary that a switching circuit be provided between an input/output (I/O) interface circuit and the memory cell matrix with the redundant cell columns.
Referring to FIG. 1, there is shown a basic model of the DRAM device with the redundant cell columns and the switching circuit. As shown in this drawing, the DRAM device comprises a memory cell matrix having a plurality of cell columns, at least one redundant cell column, a repair circuit for replacing a failed one of the cell columns of the memory cell matrix with the redundant cell column, an I/O interface circuit for inputting and outputting data between the memory device and an external device, and a pad part for applying drive signals to the repair circuit.
In FIG. 1, the repair circuit includes a plurality of npn-type transistors T1-T8, a direct current (DC) voltage source Vcc, a resistor R, an inverter I1, a plurality of repair links L1-L3 for addressing the failed one of the cell columns of the memory cell matrix, and nodes A and B. Also, the pad part includes a plurality of pads C0-C2 for applying the drive signals to the repair circuit.
Now, the operation of repairing the DRAM device in FIG. 1 will be described.
Under a normal operation, the pad C0 will go high, while the pads C1 and C2 are held low. This will turn on the transistor T4 which grounds the node B, causing the transistor T7 to be turned off and the transistors T8 and T1 to be turned on. With the pads C1 and C2 applied with a low voltage, the transistors T2 and T3 are turned off. At this time, only data from the first cell column of the memory cell matrix will be released to the node A and, since the transistor T8 is at its on state, the data will reach the I/O interface circuit.
Assume that the first cell column of the memory cell PG,4 matrix is failed. To replace the first cell column with the redundant cell column, simply blow the link L1. Now when the pad C0 goes high and the pads C1 and C2 are low, the transistors T1 and T4 are turned on; however, the transistor T4 cannot ground the node B anymore since it is no longer connected.
In this case, the node B is pulled up to a high level by the resistor R. This causes the transistor T7 to be turned on and the transistor T8 to be turned off. With the transistor T8 turned off, the data from the first cell column of the memory cell matrix cannot pass to the I/O interface circuit. Instead, the data from the redundant cell column is released through the transistor T7 to the I/O interface circuit. Therefore, the redundant cell column is used instead of the failed cell column of the memory cell matrix.
Although only one redundant cell column has been used for the illustrative purpose in FIG. 1, a plurality of redundant cell columns may be used against the case where one or more of the cell columns of the memory cell matrix are failed.
If this single link redundancy scheme as shown in FIG. 1 were implemented on a device with 64 columns, it would be necessary to have 64 switching devices like the transistors T4, T5 and T8 to repair one column, one for each column. Also, 64 links would be necessary. Here, the use of the links should be noted.
As mentioned above, the links are used to grant an address of the failed cell column to the redundant cell column when the failed cell column is replaced with the redundant cell column. In this connection, a set of the links may be referred to as an address decoder.
A conventional address decoder for repair of a 1 mega DRAM will hereinafter be described with reference to FIGS. 2a and 2b.
FIG. 2a is a view illustrating the 1 mega DRAM with 3 redundant cell columns for repair and a conventional repair circuit therefor. As shown in this drawing, the 1 mega DRAM device comprises a 1 mega memory cell matrix 1 having 1024.times.1024 cells, a redundant cell matrix 2 having the 3 redundant cell columns, a matrix address decoder 3 being applied with a DC voltage Vcc and for addressing cell columns of the 1 mega memory cell matrix 1, and a repair address decoder 4 for granting an address of a failed one of the cell columns of the 1 mega memory cell matrix 1 to a corresponding one of the redundant cell columns of the redundant cell matrix 2 to be replaced for the failed cell column.
The matrix address decoder 3 is adapted to generate an address for applying the DC voltage Vcc selectively to the cell columns of the memory cell matrix 1. In FIG. 2, each cell column has 1024 cells and cannot be used when at least one of the cells is failed. Therefore, the failure in the DRAM is repaired by replacing the failed cell column with a corresponding one of the redundant cell columns of the redundant cell matrix 2. In order to replace the failed cell column of the memory cell matrix 1 with a corresponding one of the redundant cell columns of the redundant cell matrix 2, the repair address decoder 4 is adapted to grant an address of the failed cell column to a corresponding one of the redundant cell columns.
Now, the operation of granting the address will be described with reference to FIG. 2b.
FIG. 2b is a view illustrating a construction of the repair address decoder 4. A 10-bit signal is required to address the 1 mega DRAM in FIG. 2a since the number of the columns are 2.sup.10 or 1024. The repair address decoder 4 has a plurality of links or fuses, more particularly 10 links or fuses to address each redundant cell column in the 1 mega DRAM in FIG. 2a. For this reason, the repair address decoder 4 must have 30 links since the redundant cell matrix 2 has the 3 redundant cell columns.
In FIG. 2b, addressing only one redundant cell column is illustrated as an example. Namely, the repair address decoder 4 is shown to comprise a conductive line 5 connected to the DC voltage source Vcc and 10 linear links or fuses L10-L100 connected between the conductive line 5 and the matrix address decoder 3 and spaced apart from each other at a predetermined distance.
In operation, in the case where the third cell column of the memory cell matrix 1 in FIG. 2a is failed, the repair address decoder 4 generates an address "1100000000". This address is generated by maintaining the first and second links L10 and L20 natural while blowing the remaining links as shown in FIG. 2c. Then, upon application of the DC voltage Vcc to the conductive line 5, the address "1100000000" is applied to the matrix address decoder 3, thereby causing the redundant cell column with the address to be used instead of the failed third cell column.
A laser beam is used to blow the 8 links L30-L100 linearly connected between the conductive line 5 applied with the DC voltage Vcc and the matrix address decoder 3. The links L30-L100 are instantaneously heated and thus evaporated, when centers thereof are instantaneously scanned by the laser beam. In this manner, the links L30-L100 are blown.
However, the conventional repair address decoder has a disadvantage in that only one of the links is blown by once scanning of the laser beam since the links are arranged linearly and spaced apart from each other at the predetermined distance. Namely, in the conventional repair address decoder, the scanning of the laser beam must be tried eight times to blow all the links. As a result, the more links used, the more working time required in repairing the failed cell column using the laser beam. This results in a degradation in the working efficiency and a reduction in the productivity. Further, the more number of times that the links are blown by the laser beam increases a probability that the repair is failed.